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author | Stephen Tozer <Stephen.Tozer@Sony.com> | 2022-09-15 11:26:57 +0100 |
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committer | Stephen Tozer <Stephen.Tozer@Sony.com> | 2023-01-06 18:03:48 +0000 |
commit | e10e936315410abd222eb58911b1e20fbfa80baf (patch) | |
tree | a30eec4a4b1e7413b842c0323a461e3a1b791ba4 /llvm/lib/CodeGen/MIRPrinter.cpp | |
parent | bdf7da280f624c53e6184d0410041220a9b405a7 (diff) | |
download | llvm-e10e936315410abd222eb58911b1e20fbfa80baf.zip llvm-e10e936315410abd222eb58911b1e20fbfa80baf.tar.gz llvm-e10e936315410abd222eb58911b1e20fbfa80baf.tar.bz2 |
[DebugInfo][NFC] Add new MachineOperand type and change DBG_INSTR_REF syntax
This patch makes two notable changes to the MIR debug info representation,
which result in different MIR output but identical final DWARF output (NFC
w.r.t. the full compilation). The two changes are:
* The introduction of a new MachineOperand type, MO_DbgInstrRef, which
consists of two unsigned numbers that are used to index an instruction
and an output operand within that instruction, having a meaning
identical to first two operands of the current DBG_INSTR_REF
instruction. This operand is only used in DBG_INSTR_REF (see below).
* A change in syntax for the DBG_INSTR_REF instruction, shuffling the
operands to make it resemble DBG_VALUE_LIST instead of DBG_VALUE,
and replacing the first two operands with a single MO_DbgInstrRef-type
operand.
This patch is the first of a set that will allow DBG_INSTR_REF
instructions to refer to multiple machine locations in the same manner
as DBG_VALUE_LIST.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D129372
Diffstat (limited to 'llvm/lib/CodeGen/MIRPrinter.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MIRPrinter.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index fa29c56..0f4a8a2 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -910,6 +910,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, case MachineOperand::MO_IntrinsicID: case MachineOperand::MO_Predicate: case MachineOperand::MO_BlockAddress: + case MachineOperand::MO_DbgInstrRef: case MachineOperand::MO_ShuffleMask: { unsigned TiedOperandIdx = 0; if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef()) |