GlobalISel: disambiguate types when printing MIR

Some generic instructions have multiple types. While in theory these always be
discovered by inspecting the single definition of each generic vreg, in
practice those definitions won't always be local and traipsing through a big
function to find them will not be fun.

So this changes MIRPrinter to print out the type of uses as well as defs, if
they're known to be different or not known to be the same.

On the parsing side, we're a little more flexible: provided each register is
given a type in at least one place it's mentioned (and all types are
consistent) we accept the MIR. This doesn't introduce ambiguity but makes
writing tests manually a bit less painful.

llvm-svn: 281204

1 files changed, 2 insertions, 2 deletions

diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index e7fdcc0..104d7d1 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -415,7 +415,7 @@ bool MIRParserImpl::initializeRegisterInfo(PerFunctionMIParsingState &PFS,
     if (StringRef(VReg.Class.Value).equals("_")) {
       // This is a generic virtual register.
       // The size will be set appropriately when we reach the definition.
-      Reg = RegInfo.createGenericVirtualRegister(LLT::scalar(1));
+      Reg = RegInfo.createGenericVirtualRegister(LLT{});
       PFS.GenericVRegs.insert(Reg);
     } else {
       const auto *RC = getRegClass(MF, VReg.Class.Value);
@@ -428,7 +428,7 @@ bool MIRParserImpl::initializeRegisterInfo(PerFunctionMIParsingState &PFS,
               VReg.Class.SourceRange.Start,
               Twine("use of undefined register class or register bank '") +
                   VReg.Class.Value + "'");
-        Reg = RegInfo.createGenericVirtualRegister(LLT::scalar(1));
+        Reg = RegInfo.createGenericVirtualRegister(LLT{});
         RegInfo.setRegBank(Reg, *RegBank);
         PFS.GenericVRegs.insert(Reg);
       }