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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2014-12-01 20:59:00 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2014-12-01 20:59:00 +0000 |
| commit | d0ce058f2ce944d32ad140465b6a74316510d269 (patch) | |
| tree | 99a76cf463da49cea58f438a76dd6bda5a102fdc /llvm/lib/CodeGen/LocalStackSlotAllocation.cpp | |
| parent | 879463206e16eb0a03dd86c14aeba792355dea47 (diff) | |
| download | llvm-d0ce058f2ce944d32ad140465b6a74316510d269.zip llvm-d0ce058f2ce944d32ad140465b6a74316510d269.tar.gz llvm-d0ce058f2ce944d32ad140465b6a74316510d269.tar.bz2 | |
[AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR".
r208210 introduced an optimization that improves the vector select
codegen by doing the setcc on vectors directly.
This is a problem they the setcc operands are i1s, because the
optimization would create vectors of i1, which aren't legal.
Part of PR21549.
Differential Revision: http://reviews.llvm.org/D6308
llvm-svn: 223075
Diffstat (limited to 'llvm/lib/CodeGen/LocalStackSlotAllocation.cpp')
0 files changed, 0 insertions, 0 deletions