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| author | Craig Topper <craig.topper@intel.com> | 2019-06-06 21:00:04 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-06-06 21:00:04 +0000 |
| commit | f320f2671674d0e69bf03f639762abb830a058ed (patch) | |
| tree | 4de8798910729cd10d4a811c6d6882f0e5d5db42 /llvm/lib/CodeGen/LiveDebugVariables.cpp | |
| parent | 980d3645df4509ad6e46737a41637427f254e501 (diff) | |
| download | llvm-f320f2671674d0e69bf03f639762abb830a058ed.zip llvm-f320f2671674d0e69bf03f639762abb830a058ed.tar.gz llvm-f320f2671674d0e69bf03f639762abb830a058ed.tar.bz2 | |
[X86] Make a bunch of merge masked binops commutable for loading folding.
This primarily affects add/fadd/mul/fmul/and/or/xor/pmuludq/pmuldq/max/min/fmaxc/fminc/pmaddwd/pavg.
We already commuted the unmasked and zero masked versions.
I've added 512-bit stack folding tests for most of the instructions
affected. I've tested needing commuting and not commuting across
unmasked, merged masked, and zero masked. The 128/256 bit instructions
should behave similarly.
llvm-svn: 362746
Diffstat (limited to 'llvm/lib/CodeGen/LiveDebugVariables.cpp')
0 files changed, 0 insertions, 0 deletions