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| author | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-02-09 13:55:25 +0000 |
|---|---|---|
| committer | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-02-09 13:55:25 +0000 |
| commit | dc66ae78c68f7a3094d4667bc103a216d2bd52ac (patch) | |
| tree | 7edfbb59c4f4e5d0509cdc0ed25a915c8c311610 /llvm/lib/CodeGen/LiveDebugVariables.cpp | |
| parent | b6ad25cd4ce8df28a8c0f86386f6e60e44ea5d1c (diff) | |
| download | llvm-dc66ae78c68f7a3094d4667bc103a216d2bd52ac.zip llvm-dc66ae78c68f7a3094d4667bc103a216d2bd52ac.tar.gz llvm-dc66ae78c68f7a3094d4667bc103a216d2bd52ac.tar.bz2 | |
[SelectionDAG] Provide adequate register class for RegisterSDNode
When adding operands to machine instructions in case of
RegisterSDNodes, generate a COPY node in case the register class
does not match the one in the instruction definition.
Differental Revision: https://reviews.llvm.org/D35561
llvm-svn: 324733
Diffstat (limited to 'llvm/lib/CodeGen/LiveDebugVariables.cpp')
0 files changed, 0 insertions, 0 deletions