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authorRoman Lebedev <lebedev.ri@gmail.com>2019-05-18 12:59:56 +0000
committerRoman Lebedev <lebedev.ri@gmail.com>2019-05-18 12:59:56 +0000
commit822b9c971be6784fe3dc04f4a7926834c1c818d3 (patch)
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parentf40c18b628f3b0008acf4f9ac0102f103b690cc2 (diff)
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UpdateTestChecks: arm64-eabi handlind
Summary: Was looking into supporting `(srl (shl x, c1), c2)` with c1 != c2 in dagcombiner, this test changes, but makes `update_llc_test_checks.py` unhappy Reviewers: RKSimon Reviewed By: RKSimon Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62097 llvm-svn: 361100
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