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| author | Gadi Haber <gadi.haber@intel.com> | 2017-09-19 06:19:27 +0000 |
|---|---|---|
| committer | Gadi Haber <gadi.haber@intel.com> | 2017-09-19 06:19:27 +0000 |
| commit | 6f8fbf4b868394bac2b18403b39170b76586c00a (patch) | |
| tree | a32ba5d31300f0a9d52a47298b4c4a414ce81153 /llvm/lib/CodeGen/LiveDebugVariables.cpp | |
| parent | c38371492fd24a4fa031246fc841f1ea4b197116 (diff) | |
| download | llvm-6f8fbf4b868394bac2b18403b39170b76586c00a.zip llvm-6f8fbf4b868394bac2b18403b39170b76586c00a.tar.gz llvm-6f8fbf4b868394bac2b18403b39170b76586c00a.tar.bz2 | |
[X86][Skylake] Adding the scheduling information for the SkylakeClient target
This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target.
We used the scheduling information retrieved from the Skylake architects in order to create the file.
The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction.
The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879.
Please expect some performance fluctuations due to code alignment effects.
Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena
Differential Revision: https://reviews.llvm.org/D37294
llvm-svn: 313613
Diffstat (limited to 'llvm/lib/CodeGen/LiveDebugVariables.cpp')
0 files changed, 0 insertions, 0 deletions