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| author | Durgadoss R <durgadossr@nvidia.com> | 2025-01-23 16:15:52 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-23 16:15:52 +0530 |
| commit | 2e6cc79f816d942ab09d6a310cd925c1da148aa9 (patch) | |
| tree | 5699bafcf70e2148116705423f1b8a976ddac0db /llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | |
| parent | cad6bbade0d7dc57b9c43d9ed8c38260345d50bf (diff) | |
| download | llvm-2e6cc79f816d942ab09d6a310cd925c1da148aa9.zip llvm-2e6cc79f816d942ab09d6a310cd925c1da148aa9.tar.gz llvm-2e6cc79f816d942ab09d6a310cd925c1da148aa9.tar.bz2 | |
[MLIR][NVVM] Migrate CpAsyncOp to intrinsics (#123789)
Intrinsics are available for the 'cpSize'
variants also. So, this patch migrates the Op
to lower to the intrinsics for all cases.
* Update the existing tests to check the lowering to intrinsics.
* Add newer cp_async_zfill tests to verify the lowering for the 'cpSize'
variants.
* Tidy-up CHECK lines in cp_async() function in nvvmir.mlir (NFC)
PTX spec link:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async
Signed-off-by: Durgadoss R <durgadossr@nvidia.com>
Diffstat (limited to 'llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp')
0 files changed, 0 insertions, 0 deletions