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| author | Craig Topper <craig.topper@intel.com> | 2020-03-03 12:16:01 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-03-03 12:16:03 -0800 |
| commit | 02f03a6fd4cd64730e6229e0202404d90079b8d1 (patch) | |
| tree | 5f268be71c4644a530be47bcb5ce87835daa6b47 /llvm/lib/CodeGen/LiveDebugValues.cpp | |
| parent | 1bedb2340774099fd3faa6610a78119a4f802955 (diff) | |
| download | llvm-02f03a6fd4cd64730e6229e0202404d90079b8d1.zip llvm-02f03a6fd4cd64730e6229e0202404d90079b8d1.tar.gz llvm-02f03a6fd4cd64730e6229e0202404d90079b8d1.tar.bz2 | |
[X86] Match vpmullq latency to uops.info. Correct port usage for 512-bit memory form
uops.info says these should be 15 cycle instructions. Uops.info also shows the 512-bit form uses port 0 and 5 for both register and memory. We had memory using 0 and 1.
Differential Revision: https://reviews.llvm.org/D75549
Diffstat (limited to 'llvm/lib/CodeGen/LiveDebugValues.cpp')
0 files changed, 0 insertions, 0 deletions