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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-06-20 20:39:23 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-06-20 20:39:23 +0000 |
| commit | da448fe0b19ae32b950af6725e24864876ec5170 (patch) | |
| tree | 6cfdef5ea6a78ef015455545d2c9e3cd402967f0 /llvm/lib/CodeGen/InterferenceCache.cpp | |
| parent | 93b9ecba9bb24d2c9087e8044f76097b3b882011 (diff) | |
| download | llvm-da448fe0b19ae32b950af6725e24864876ec5170.zip llvm-da448fe0b19ae32b950af6725e24864876ec5170.tar.gz llvm-da448fe0b19ae32b950af6725e24864876ec5170.tar.bz2 | |
In MipsDisassembler.cpp, instead of defining register class tables, use the ones
that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.
Also, fix bug in function DecodeAFGR64RegisterClass.
Patch by Vladimir Medic.
llvm-svn: 158846
Diffstat (limited to 'llvm/lib/CodeGen/InterferenceCache.cpp')
0 files changed, 0 insertions, 0 deletions