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| author | Christudasan Devadasan <christudasan.devadasan@amd.com> | 2023-11-16 10:30:03 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-16 10:30:03 +0530 |
| commit | ce7fd498ed91344c23f0864bbd5b84d65eaae3ef (patch) | |
| tree | 0d297ede1e4b78147282db94e2e169eaf97cbabc /llvm/lib/CodeGen/InlineSpiller.cpp | |
| parent | e8fc282ff26b4d1d71a316bf036fc486b420ea19 (diff) | |
| download | llvm-ce7fd498ed91344c23f0864bbd5b84d65eaae3ef.zip llvm-ce7fd498ed91344c23f0864bbd5b84d65eaae3ef.tar.gz llvm-ce7fd498ed91344c23f0864bbd5b84d65eaae3ef.tar.bz2 | |
[AMDGPU] RA inserted scalar instructions can be at the BB top (#72140)
We adjust the insertion point at the BB top for spills/copies during RA
to ensure they are placed after the exec restore instructions required
for the divergent control flow execution. This is, however, required
only for the vector operations. The insertions for scalar registers can
still go to the BB top.
Diffstat (limited to 'llvm/lib/CodeGen/InlineSpiller.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/InlineSpiller.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index 71d58b2..2740265 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -469,7 +469,7 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI, MachineBasicBlock *MBB = LIS.getMBBFromIndex(SrcVNI->def); MachineBasicBlock::iterator MII; if (SrcVNI->isPHIDef()) - MII = MBB->SkipPHIsLabelsAndDebug(MBB->begin()); + MII = MBB->SkipPHIsLabelsAndDebug(MBB->begin(), SrcReg); else { MachineInstr *DefMI = LIS.getInstructionFromIndex(SrcVNI->def); assert(DefMI && "Defining instruction disappeared"); |