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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2023-10-20 00:51:12 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-10-20 00:51:12 +0900 |
| commit | 3e49ce6ea16ec7e1c580ab785992b773a37f270c (patch) | |
| tree | b0b32f8f97972a4fd7aad0fcb9efa1e37df7e2f9 /llvm/lib/CodeGen/InlineSpiller.cpp | |
| parent | d2e7a15dfb509393d8eb74e1bb4348e72a92dfcd (diff) | |
| download | llvm-3e49ce6ea16ec7e1c580ab785992b773a37f270c.zip llvm-3e49ce6ea16ec7e1c580ab785992b773a37f270c.tar.gz llvm-3e49ce6ea16ec7e1c580ab785992b773a37f270c.tar.bz2 | |
InlineSpiller: Delete assert that implicit_def has no implicit operands (#69087)
It's not a verifier enforced property that implicit_def may only have
one operand. Fixes assertions after the coalescer implicit-defs to
preserve super register liveness to arbitrary instructions.
For some reason I'm unable to reproduce this as a MIR test running only
the allocator for the x86 test. Not sure it's worth keeping around.
Diffstat (limited to 'llvm/lib/CodeGen/InlineSpiller.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/InlineSpiller.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index c62f3db..46fcc62 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -1071,8 +1071,7 @@ void InlineSpiller::insertReload(Register NewVReg, static bool isRealSpill(const MachineInstr &Def) { if (!Def.isImplicitDef()) return true; - assert(Def.getNumOperands() == 1 && - "Implicit def with more than one definition"); + // We can say that the VReg defined by Def is undef, only if it is // fully defined by Def. Otherwise, some of the lanes may not be // undef and the value of the VReg matters. |