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| author | Chris Dewhurst <chris.dewhurst@lero.ie> | 2016-02-27 12:49:59 +0000 |
|---|---|---|
| committer | Chris Dewhurst <chris.dewhurst@lero.ie> | 2016-02-27 12:49:59 +0000 |
| commit | 053826af69fc8e5ffd0551eb965c33413f0e6f45 (patch) | |
| tree | 8784057eefafa8df7abdabc2fe129aa944ce6ba1 /llvm/lib/CodeGen/DFAPacketizer.cpp | |
| parent | a9a7bf68ee35ffbe2fd6a8ac06290f24f94e16f9 (diff) | |
| download | llvm-053826af69fc8e5ffd0551eb965c33413f0e6f45.zip llvm-053826af69fc8e5ffd0551eb965c33413f0e6f45.tar.gz llvm-053826af69fc8e5ffd0551eb965c33413f0e6f45.tar.bz2 | |
The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual.
These are all co-processor registers, with the exception of the floating-point deferred-trap queue register.
Although these will not be lowered automatically by any instructions, it allows the use of co-processor
instructions implemented by inline-assembly.
Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td,
which was formerly causing a problem in the disassembly of the %fq register.
llvm-svn: 262133
Diffstat (limited to 'llvm/lib/CodeGen/DFAPacketizer.cpp')
0 files changed, 0 insertions, 0 deletions