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author | David Green <david.green@arm.com> | 2021-11-30 11:05:32 +0000 |
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committer | David Green <david.green@arm.com> | 2021-11-30 11:05:32 +0000 |
commit | 52ff3b009388f1bef4854f1b6470b4ec19d10b0e (patch) | |
tree | 692b21c438c47e7e6027ebe45237907401312dec /llvm/lib/CodeGen/CommandFlags.cpp | |
parent | a34f24689945e967e4ba4d79ed301d3a71870c7b (diff) | |
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[DAG] Create fptosi.sat from clamped fptosi
This adds a fold in DAGCombine to create fptosi_sat from sequences for
smin(smax(fptosi(x))) nodes, where the min/max saturate the output of
the fp convert to a specific bitwidth (say INT_MIN and INT_MAX). Because
it is dealing with smin(/smax) in DAG they may currently be ISD::SMIN,
ISD::SETCC/ISD::SELECT, ISD::VSELECT or ISD::SELECT_CC nodes which need
to be handled similarly.
A shouldConvertFpToSat method was added to control when converting may
be profitable. The original fptosi will have a less strict semantics
than the fptosisat, with less values that need to produce defined
behaviour.
This especially helps on ARM/AArch64 where the vcvt instructions
naturally saturate the result.
Differential Revision: https://reviews.llvm.org/D111976
Diffstat (limited to 'llvm/lib/CodeGen/CommandFlags.cpp')
0 files changed, 0 insertions, 0 deletions