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| author | Anton Sidorenko <anton.sidorenko@syntacore.com> | 2024-06-21 11:40:10 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-21 11:40:10 +0300 |
| commit | d59a4cac5fe6c05da0e9088aad8f94c207423c36 (patch) | |
| tree | df20dc2be13aa8ea3e01fdcac390e0c3f7250f9e /llvm/lib/CodeGen/CodeGenPrepare.cpp | |
| parent | 7c946f04cf363a8c581529907be8ee9f735591c7 (diff) | |
| download | llvm-d59a4cac5fe6c05da0e9088aad8f94c207423c36.zip llvm-d59a4cac5fe6c05da0e9088aad8f94c207423c36.tar.gz llvm-d59a4cac5fe6c05da0e9088aad8f94c207423c36.tar.bz2 | |
[RISCV] Add Syntacore SCR3 processor definition (#95953)
Syntacore SCR3 is a microcontroller-class processor core. Overview:
https://syntacore.com/products/scr3
This PR introduces two CPUs:
* 'syntacore-scr3-rv32' which is rv32imc
* 'syntacore-scr3-rv64' which is rv64imac
---------
Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Diffstat (limited to 'llvm/lib/CodeGen/CodeGenPrepare.cpp')
0 files changed, 0 insertions, 0 deletions