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| author | Sanjay Patel <spatel@rotateright.com> | 2020-05-23 10:13:50 -0400 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2020-05-24 09:19:47 -0400 |
| commit | 7eed772a279e8cd45eee70cab2cfa71f71cc90c8 (patch) | |
| tree | 22f0151dbfd18dd69d235eac10f85adc752c8866 /llvm/lib/CodeGen/CodeGenPrepare.cpp | |
| parent | b05b69e056adfa95f8bbb92b541247eb0ba055ee (diff) | |
| download | llvm-7eed772a279e8cd45eee70cab2cfa71f71cc90c8.zip llvm-7eed772a279e8cd45eee70cab2cfa71f71cc90c8.tar.gz llvm-7eed772a279e8cd45eee70cab2cfa71f71cc90c8.tar.bz2 | |
[PatternMatch] abbreviate vector inst matchers; NFC
Readability is not reduced with these opcodes/match lines,
so reduce odds of awkward wrapping from 80-col limit.
Diffstat (limited to 'llvm/lib/CodeGen/CodeGenPrepare.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/CodeGenPrepare.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index e04fb25..d4c471af 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -6460,9 +6460,8 @@ bool CodeGenPrepare::optimizeSelectInst(SelectInst *SI) { /// in MVE takes a GPR (integer) register, and the instruction that incorporate /// a VDUP (such as a VADD qd, qm, rm) also require a gpr register. bool CodeGenPrepare::optimizeShuffleVectorInst(ShuffleVectorInst *SVI) { - if (!match(SVI, - m_ShuffleVector(m_InsertElement(m_Undef(), m_Value(), m_ZeroInt()), - m_Undef(), m_ZeroMask()))) + if (!match(SVI, m_Shuffle(m_InsertElt(m_Undef(), m_Value(), m_ZeroInt()), + m_Undef(), m_ZeroMask()))) return false; Type *NewType = TLI->shouldConvertSplatType(SVI); if (!NewType) |