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| author | Diana Picus <Diana-Magda.Picus@amd.com> | 2025-03-10 05:07:56 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-10 05:07:56 +0100 |
| commit | 3e94eae746888ee63b38d347b068eaf0d5b72772 (patch) | |
| tree | 08b66fb74b515de807cac91c34a85540ca0e11d0 /llvm/lib/CodeGen/CodeGenPrepare.cpp | |
| parent | fa45bf430081ed5a37c50719dfd3a8ca32271126 (diff) | |
| download | llvm-3e94eae746888ee63b38d347b068eaf0d5b72772.zip llvm-3e94eae746888ee63b38d347b068eaf0d5b72772.tar.gz llvm-3e94eae746888ee63b38d347b068eaf0d5b72772.tar.bz2 | |
[AMDGPU] Add GFX12 S_ALLOC_VGPR instruction (#130018)
This patch only adds the instruction for disassembly support.
We neither have an instrinsic nor codegen support, and it is unclear
whether we actually want to ever have an intrinsic, given the fragile
semantics.
For now, it will be generated only by the backend in very specific
circumstances.
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Co-authored-by: Jannik Silvanus <jannik.silvanus@amd.com>
Diffstat (limited to 'llvm/lib/CodeGen/CodeGenPrepare.cpp')
0 files changed, 0 insertions, 0 deletions