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| author | Craig Topper <craig.topper@intel.com> | 2019-01-30 19:57:01 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-01-30 19:57:01 +0000 |
| commit | 22b3de5b51f2d98252744217f45adaadeabec9da (patch) | |
| tree | 382575935396f75cf343f172747b67b66c391612 /llvm/lib/CodeGen/CodeGenPrepare.cpp | |
| parent | e171ade25c9b7904f88ca8a370fcc7ced5671602 (diff) | |
| download | llvm-22b3de5b51f2d98252744217f45adaadeabec9da.zip llvm-22b3de5b51f2d98252744217f45adaadeabec9da.tar.gz llvm-22b3de5b51f2d98252744217f45adaadeabec9da.tar.bz2 | |
[X86] Mark EMMS and FEMMS as clobbering MM0-7 and ST0-7.
This fixes the test case in PR35982 by preventing MMX instructions that read MM0-7 from being moved below EMMS/FEMMS by the post RA scheduler.
Though as discussed in bugzilla, this is not a complete fix. There is still the possibility of reordering in IR or by the pre-RA scheduler.
Differential Revision: https://reviews.llvm.org/D57298
llvm-svn: 352660
Diffstat (limited to 'llvm/lib/CodeGen/CodeGenPrepare.cpp')
0 files changed, 0 insertions, 0 deletions