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| author | Anton Afanasyev <anton.a.afanasyev@gmail.com> | 2021-08-12 14:51:57 +0300 |
|---|---|---|
| committer | Anton Afanasyev <anton.a.afanasyev@gmail.com> | 2021-08-17 12:44:37 +0300 |
| commit | 1f3e35b6d165715ec7bf7ba80d5b982719c7752a (patch) | |
| tree | f25b5ab0f880fb627b30e45bb1b435c317b0d38a /llvm/lib/CodeGen/CodeGenPrepare.cpp | |
| parent | 8f8f9260a95f784e8c4620d652986724ac1b88df (diff) | |
| download | llvm-1f3e35b6d165715ec7bf7ba80d5b982719c7752a.zip llvm-1f3e35b6d165715ec7bf7ba80d5b982719c7752a.tar.gz llvm-1f3e35b6d165715ec7bf7ba80d5b982719c7752a.tar.bz2 | |
[AggressiveInstCombine] Add shift left instruction to `TruncInstCombine` DAG
Add `shl` instruction to the DAG post-dominated by `trunc`, allowing
TruncInstCombine to reduce bitwidth of expressions containing left shifts.
The only thing we need to check is that the target bitwidth must be wider
than the maximal shift amount: https://alive2.llvm.org/ce/z/AwArqu
Part of https://reviews.llvm.org/D107766
Differential Revision: https://reviews.llvm.org/D108091
Diffstat (limited to 'llvm/lib/CodeGen/CodeGenPrepare.cpp')
0 files changed, 0 insertions, 0 deletions