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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2025-10-07 09:31:07 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-07 09:31:07 -0700 |
| commit | a280db60c8cc8f10225fee3e2385ff1704528b6e (patch) | |
| tree | 9451e0263a548a57dd27b786ba0d5dd1fdf69e01 /llvm/lib/CodeGen/CodeGen.cpp | |
| parent | 93097b2d47c87bf5eee0a2612d961c7a01831eab (diff) | |
| download | llvm-a280db60c8cc8f10225fee3e2385ff1704528b6e.zip llvm-a280db60c8cc8f10225fee3e2385ff1704528b6e.tar.gz llvm-a280db60c8cc8f10225fee3e2385ff1704528b6e.tar.bz2 | |
[AMDGPU] Use true16 loads with +real-true16 and sram-ecc (#161256)
When sram-ecc is enabled 16-bit loads clobber full 32-bit VGPR.
A load into a just 16-bit VGPR is not possible. Do a 16-bit
extending load and extract a 16-bit subreg in this situation.
Also fixes lack of 16-bit store patterns with this combination.
Fixes: SC1-6072
Diffstat (limited to 'llvm/lib/CodeGen/CodeGen.cpp')
0 files changed, 0 insertions, 0 deletions