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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-11-26 23:29:11 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-26 23:29:11 -0500 |
| commit | 142b33c58b26aae4d27f3f063eb492256beda3a6 (patch) | |
| tree | 30ff91c93821c18181eaaa58dc1bb47bed1b2f21 /llvm/lib/CodeGen/CodeGen.cpp | |
| parent | 265e209ceba8c330403d77f46a33b8e138c5633f (diff) | |
| download | llvm-142b33c58b26aae4d27f3f063eb492256beda3a6.zip llvm-142b33c58b26aae4d27f3f063eb492256beda3a6.tar.gz llvm-142b33c58b26aae4d27f3f063eb492256beda3a6.tar.bz2 | |
AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (#117822)
For multipass instructions, overlap on VDST and SRC’s
would result in HW race & undefined results.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap@amd.com>
Diffstat (limited to 'llvm/lib/CodeGen/CodeGen.cpp')
0 files changed, 0 insertions, 0 deletions