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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-04-11 11:20:04 +0100 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-04-11 11:20:09 +0100 |
| commit | 058a33d3c9249e9475cf1e42b9721251e816cd47 (patch) | |
| tree | 8e6ea61661b846e76f949eb472eecee4ec64e5a5 /llvm/lib/CodeGen/CodeGen.cpp | |
| parent | b72fd1a84d33e19f9f7fa6b7fdcaea57dc51aee4 (diff) | |
| download | llvm-058a33d3c9249e9475cf1e42b9721251e816cd47.zip llvm-058a33d3c9249e9475cf1e42b9721251e816cd47.tar.gz llvm-058a33d3c9249e9475cf1e42b9721251e816cd47.tar.bz2 | |
[X86] Account for high uop/resource usage in BSF/BSR instructions
znver1/2 models were incorrectly modelling these as single uop instructions, instead of the microcoded nightmares they really are.
Now matches AMD SoG, Agner and instlatx64 numbers.
Fixes #54811
Diffstat (limited to 'llvm/lib/CodeGen/CodeGen.cpp')
0 files changed, 0 insertions, 0 deletions