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| author | quic_hchandel <quic_hchandel@quicinc.com> | 2025-08-14 12:08:28 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-14 12:08:28 +0530 |
| commit | 71b066e3a2512d582e34a0b5257e12b1177d4bcc (patch) | |
| tree | c852bc7ac82515355efcf23b86991ae9c46a3b91 /llvm/lib/CodeGen/BranchFolding.cpp | |
| parent | ab5a5a90c03d25392fcc486a8c587d0dd9b7a0c6 (diff) | |
| download | llvm-71b066e3a2512d582e34a0b5257e12b1177d4bcc.zip llvm-71b066e3a2512d582e34a0b5257e12b1177d4bcc.tar.gz llvm-71b066e3a2512d582e34a0b5257e12b1177d4bcc.tar.bz2 | |
[RISCV] Add CodeGen support for qc.insbi and qc.insb insert instructions (#152447)
This patch adds CodeGen support for qc.insbi and qc.insb instructions
defined in the Qualcomm uC Xqcibm extension. qc.insbi and qc.insb
inserts bits into destination register from immediate and register
operand respectively.
A sequence of `xor`, `and` & `xor` depending on appropriate conditions
are converted to `qc.insbi` or `qc.insb` which depends on the
immediate's value.
Diffstat (limited to 'llvm/lib/CodeGen/BranchFolding.cpp')
0 files changed, 0 insertions, 0 deletions