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| author | Michael Maitland <michaeltmaitland@gmail.com> | 2022-11-03 14:30:58 -0700 |
|---|---|---|
| committer | Michael Maitland <michaeltmaitland@gmail.com> | 2022-12-06 16:57:35 -0800 |
| commit | 7b3650285442f0c1cf7f7417706c0c66f9b5262c (patch) | |
| tree | ec9582e033fb00efc78f6d473337e5c380babf69 /llvm/lib/CodeGen/BasicBlockSections.cpp | |
| parent | 1a43227ba595aea18bc4ae323fae729883b4d5fb (diff) | |
| download | llvm-7b3650285442f0c1cf7f7417706c0c66f9b5262c.zip llvm-7b3650285442f0c1cf7f7417706c0c66f9b5262c.tar.gz llvm-7b3650285442f0c1cf7f7417706c0c66f9b5262c.tar.bz2 | |
[RISCV][CodeGen] Account for LMUL for Vector Integer load store instructions
It is likley that subtargets act differently for a vector load store instructions based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.
Differential Revision: https://reviews.llvm.org/D137429
Diffstat (limited to 'llvm/lib/CodeGen/BasicBlockSections.cpp')
0 files changed, 0 insertions, 0 deletions