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| author | lakshayk-nv <lakshayk@nvidia.com> | 2025-03-06 14:32:54 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-06 09:02:54 +0000 |
| commit | d61d2197390161db86b48d044970f48132139ccb (patch) | |
| tree | 98c5d5dc8810fc9cb8d2687100411254d0d5877d /llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp | |
| parent | a2b05761724e5243056988d9d6bf1a5a94715b74 (diff) | |
| download | llvm-d61d2197390161db86b48d044970f48132139ccb.zip llvm-d61d2197390161db86b48d044970f48132139ccb.tar.gz llvm-d61d2197390161db86b48d044970f48132139ccb.tar.bz2 | |
Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (#127564)
Current implementation (for Aarch64) in llvm-exegesis only supports
GRP32 and GPR64 bit register class, thus for opcodes variants which used
FPR64/128, PPR16 and ZPR128, llvm-exegesis throws warning "setReg is not
implemented". This code will handle the above register class and
initialize the registers using appropriate base instruction class.
Diffstat (limited to 'llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions