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| author | Mallikarjuna Gouda <mgouda@mips.com> | 2025-05-04 10:48:19 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-04 01:18:19 -0400 |
| commit | c22bc215ac9496ee5f6e55ba0b0904dc825c6f56 (patch) | |
| tree | ebd050702c288c0f1e8205d7ab14da457a8cf323 /llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp | |
| parent | 2d287f51eff2a5fbf84458a33f7fb2493cf67965 (diff) | |
| download | llvm-c22bc215ac9496ee5f6e55ba0b0904dc825c6f56.zip llvm-c22bc215ac9496ee5f6e55ba0b0904dc825c6f56.tar.gz llvm-c22bc215ac9496ee5f6e55ba0b0904dc825c6f56.tar.bz2 | |
[MIPS] Reland Scheduling model for MIPS i6400 and i6500 CPUs (#132704) (#137984)
Relands #132704 with a fix in the testcase:
Add llvm/test/tools/llvm-mca/Mips/lit.local.cfg
Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6
processor.
i6400 and i6500 share same instruction latencies.
CPU has following pipelines
- Two ALUs
- Multiply and Divide unit (MDU)
- Branch Unit (CTU)
- Load/Store Unit (LSU)
- Short Floating-point Unit and
- Long Floating-point Unit
Latency information is available at:
https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf
Diffstat (limited to 'llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions