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| author | David Green <david.green@arm.com> | 2024-09-19 14:52:52 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-19 14:52:52 +0100 |
| commit | 02a1d311bde4a90cffa661215c81f9fef1bc7967 (patch) | |
| tree | 169b7f0ef2a18858477f98da7c197140d75e0a60 /llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp | |
| parent | b1b436c108101f31b27eedb3a9591b7a02e0bc6e (diff) | |
| download | llvm-02a1d311bde4a90cffa661215c81f9fef1bc7967.zip llvm-02a1d311bde4a90cffa661215c81f9fef1bc7967.tar.gz llvm-02a1d311bde4a90cffa661215c81f9fef1bc7967.tar.bz2 | |
[AArch64] Extend and rewrite load zero and load undef patterns (#108185)
The ldr instructions implicitly zero any upper lanes, so we can use them
for insert(zerovec, load, 0) patterns. Likewise insert(undef, load, 0)
or scalar_to_reg can reuse the scalar loads as the top bits are undef.
This patch makes sure there are patterns for each type and for each of
the normal, unaligned, roW and roX addressing modes.
Diffstat (limited to 'llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions