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author | Craig Topper <craig.topper@sifive.com> | 2021-09-24 14:29:55 -0700 |
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committer | Craig Topper <craig.topper@sifive.com> | 2021-09-24 15:10:25 -0700 |
commit | 715cf6ffb9a0491aa8749bf024d741de520fa1f2 (patch) | |
tree | e3a2a64f7159b4d9704c1b2e585a3ed1d290c43c /llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp | |
parent | d0649320bf39efddf10a430c1821911060d684b2 (diff) | |
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[RISCV] Add another isel optimization for (and (shl X, c2), c1).
Where c1 is a shifted mask with 32-c2 leading zeros and c3 trailing
zeros and c3>c2. We can select it as (slli (srliw X, c3-c2), c3).
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp')
0 files changed, 0 insertions, 0 deletions