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| author | Jakub Kuderski <kubak@google.com> | 2023-03-14 10:48:13 -0400 |
|---|---|---|
| committer | Jakub Kuderski <kubak@google.com> | 2023-03-14 10:59:30 -0400 |
| commit | f80a976acd85611acd795225999a92bba57c76e6 (patch) | |
| tree | 8f27bd664e521d6b0582c8bcb37e31039f1ab135 /llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | |
| parent | 4e3c8720c0da2614b25e32dd473b3fa5da3e2592 (diff) | |
| download | llvm-f80a976acd85611acd795225999a92bba57c76e6.zip llvm-f80a976acd85611acd795225999a92bba57c76e6.tar.gz llvm-f80a976acd85611acd795225999a92bba57c76e6.tar.bz2 | |
[mlir][vector] Add gather lowering patterns
This is for targets that do not support gather-like ops, e.g., SPIR-V.
Gather is expanded into lower-level vector ops with memory accesses
guarded with `scf.if`.
I also considered generating `vector.maskedload`s, but decided against
it to keep the `memref` and `tensor` codepath closer together. There's a
good chance that if a target doesn't support gather it does not support
masked loads either.
Issue: https://github.com/llvm/llvm-project/issues/60905
Reviewed By: ThomasRaoux
Differential Revision: https://reviews.llvm.org/D145942
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp')
0 files changed, 0 insertions, 0 deletions