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| author | Craig Topper <craig.topper@sifive.com> | 2023-05-16 09:43:38 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-05-16 09:43:38 -0700 |
| commit | 8f43c3f49ecea404458a2fbde126e20c6d404a14 (patch) | |
| tree | e76fb37def812af74fd23628273d74cd05d6ae94 /llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | |
| parent | 2f4c96097a3cbf9d07eab699efd25f767bb4fdd5 (diff) | |
| download | llvm-8f43c3f49ecea404458a2fbde126e20c6d404a14.zip llvm-8f43c3f49ecea404458a2fbde126e20c6d404a14.tar.gz llvm-8f43c3f49ecea404458a2fbde126e20c6d404a14.tar.bz2 | |
[RISCV] Rework how implied SP operands work in the disassembler. NFC
Previously we added the SP operands when an immediate operand was added
to certain opcodes.
This patch moves it to a post processing step using the information
in MCInstrDesc. This avoids an explicit opcode list in RISCVDisassembler.cpp.
In considered using a custom DecoderMethod, but the bit swizzling we
need to do for the immediates on these instructions made that
unattractive.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D149931
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp')
0 files changed, 0 insertions, 0 deletions