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| author | Philip Reames <preames@rivosinc.com> | 2022-05-16 16:27:39 -0700 |
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| committer | Philip Reames <preames@rivosinc.com> | 2022-05-16 16:38:30 -0700 |
| commit | 7dbf2e7b576f52f1c459665fe524d7521d560dae (patch) | |
| tree | 981eac30110fe7cc73f816400b131293ae53e42b /llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | |
| parent | 52ddae132f8ccd646e93d42b69f1efd902ecb4f2 (diff) | |
| download | llvm-7dbf2e7b576f52f1c459665fe524d7521d560dae.zip llvm-7dbf2e7b576f52f1c459665fe524d7521d560dae.tar.gz llvm-7dbf2e7b576f52f1c459665fe524d7521d560dae.tar.bz2 | |
Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)
The existing redundant copy elimination required a virtual register source, but the same logic works for any physreg where we don't have to worry about clobbers. On RISCV, this helps eliminate redundant CSR reads from VLENB.
Differential Revision: https://reviews.llvm.org/D125564
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp')
0 files changed, 0 insertions, 0 deletions