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| author | Craig Topper <craig.topper@sifive.com> | 2022-03-11 17:10:03 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-03-11 18:02:47 -0800 |
| commit | 43f668b98e8d87290fc6bbf5ed13c3ab542e3497 (patch) | |
| tree | 1cc9b7b45d53bb99d85024b5e9436313dbfb6a53 /llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | |
| parent | fa62c5326a9d74a52ed0678db470a3d759f1602a (diff) | |
| download | llvm-43f668b98e8d87290fc6bbf5ed13c3ab542e3497.zip llvm-43f668b98e8d87290fc6bbf5ed13c3ab542e3497.tar.gz llvm-43f668b98e8d87290fc6bbf5ed13c3ab542e3497.tar.bz2 | |
[RISCV] Move GORCIW/GREVIW formation to isel patterns.
Type legalize narrow RISCVISD::GREV/GORC with constant to a larger
type without switching to W. Detect sext_inreg+gorci/grevi with a
uimm5 immediate during isel to emit GREVIW/GORCIW.
This allows us to better propagate known bits information through
extended bits after type legalization. It will also simplify a
change I'm considering for BREV8 with Zbkb.
A future patch will add computeKnownBits support for GORC.
A further improvement here would be to use hasAllWUsers and
doPeepholeSExtW like we do for SLLIW, but I don't think we have
the test coverage for that yet.
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp')
0 files changed, 0 insertions, 0 deletions