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| author | Sebastian Pop <sebpop@gmail.com> | 2018-03-06 16:54:55 +0000 |
|---|---|---|
| committer | Sebastian Pop <sebpop@gmail.com> | 2018-03-06 16:54:55 +0000 |
| commit | 41073e8046d3fd52c42b2de718bad6b761cbd1ac (patch) | |
| tree | 8fac35b4fe4a7190bf81ddca0be552c8c000e290 /llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | |
| parent | 44681074ceae90806538a0adc55ed3ab93768a52 (diff) | |
| download | llvm-41073e8046d3fd52c42b2de718bad6b761cbd1ac.zip llvm-41073e8046d3fd52c42b2de718bad6b761cbd1ac.tar.gz llvm-41073e8046d3fd52c42b2de718bad6b761cbd1ac.tar.bz2 | |
[AArch64] define isExtractSubvectorCheap
Following the ARM-neon backend, define isExtractSubvectorCheap to return true
when extracting low and high part of a neon register.
The patch disables a test in llvm/test/CodeGen/AArch64/arm64-ext.ll This
testcase is fragile in the sense that it requires a BUILD_VECTOR to "survive"
all DAG transforms until ISelLowering. The testcase is supposed to check that
AArch64TargetLowering::ReconstructShuffle() works, and for that we need a
BUILD_VECTOR in ISelLowering. As we now transform the BUILD_VECTOR earlier into
an VEXT + vector_shuffle, we don't have the BUILD_VECTOR pattern when we get to
ISelLowering. As there is no way to disable the combiner to only exercise the
code in ISelLowering, the patch disables the testcase.
Differential revision: https://reviews.llvm.org/D43973
llvm-svn: 326811
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp')
0 files changed, 0 insertions, 0 deletions