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authorPhilip Reames <preames@rivosinc.com>2022-05-16 16:40:35 -0700
committerPhilip Reames <preames@rivosinc.com>2022-05-16 17:06:27 -0700
commit3d17c917099a691e12f05d2502d81b972600a4ae (patch)
tree28c27f407e01aec09adc262fe90a88ec4346b6ea /llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
parentf20e6a6e61da83fbc444e21aa51f4794d1273bec (diff)
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[RISCV] Fix missing vsetvli in transparent block case
We've got a lurking problem with our data flow implementation where different phases disagree, resulting in possible miscompiles. D119518 introduced a workaround, but failed to consider blocks which only contain load/stores compatible with their incoming state. When I went to rebase and simplify D125232, it turned out that not all of the correctness issues had been fixed yet after all. This is the correctness fix accidentally embedded in the original more complicated version. Note that the test changes here are mostly regressions. It's worth noting that the simplified version of D125232 exactly reverses all the non-functional diffs in the test caused here. D125232 should be the immediate following commit. Differential Revision: https://reviews.llvm.org/D125703
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