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| author | David Green <david.green@arm.com> | 2023-05-16 18:30:22 +0100 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2023-05-16 18:30:22 +0100 |
| commit | 198f6a9f36e4ffd056e27fac8c0636476958d3cf (patch) | |
| tree | f466aee6d2de51d1a14c080c7f662f3ff3603986 /llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | |
| parent | 01e22dfb104e7ab4737e512d4e1bbc609962b13e (diff) | |
| download | llvm-198f6a9f36e4ffd056e27fac8c0636476958d3cf.zip llvm-198f6a9f36e4ffd056e27fac8c0636476958d3cf.tar.gz llvm-198f6a9f36e4ffd056e27fac8c0636476958d3cf.tar.bz2 | |
[AArch64] Combine add(extract v1i64) into v1i64 add
This helps fix a regression from D148309 where a shift + add was no longer
combined into a ssra. It looks for add's with v1i64 extract operands and
converts them to v1i64 adds. The other operand needs to be something that is
easily converted to a v1i64, in this case it currently just checks for a load.
Some of the code in performAddSubCombine has been cleaned up whilst I was here.
Differential Revision: https://reviews.llvm.org/D148311
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp')
0 files changed, 0 insertions, 0 deletions