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| author | Jeffrey Byrnes <jeffrey.byrnes@amd.com> | 2025-07-07 13:50:42 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-07 13:50:42 -0700 |
| commit | 0da9aacf4898fc9debfd930ab3dfbac7084c5e2a (patch) | |
| tree | 5dd707bf2114118f3fa68f27acefcb00c9427ea8 /llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | |
| parent | ff1b37b87ab8897b236da234f7b2f461004641b8 (diff) | |
| download | llvm-0da9aacf4898fc9debfd930ab3dfbac7084c5e2a.zip llvm-0da9aacf4898fc9debfd930ab3dfbac7084c5e2a.tar.gz llvm-0da9aacf4898fc9debfd930ab3dfbac7084c5e2a.tar.bz2 | |
[InstCombine] Extend bitmask mul combine to handle independent operands (#142503)
This extends https://github.com/llvm/llvm-project/pull/136013 to capture
cases where the combineable bitmask muls are nested under multiple
or-disjoints.
This PR is meant for commits starting at
8c403c912046505ffc10378560c2fc48f214af6a
op1 = or-disjoint mul(and (X, C1), D) , reg1
op2 = or-disjoint mul(and (X, C2), D) , reg2
out = or-disjoint op1, op2
->
temp1 = or-disjoint reg1, reg2
out = or-disjoint mul(and (X, (C1 + C2)), D), temp1
Case1: https://alive2.llvm.org/ce/z/dHApyV
Case2: https://alive2.llvm.org/ce/z/Jz-Nag
Case3: https://alive2.llvm.org/ce/z/3xBnEV
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp')
0 files changed, 0 insertions, 0 deletions