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| author | Artem Tamazov <artem.tamazov@amd.com> | 2016-04-13 16:18:41 +0000 |
|---|---|---|
| committer | Artem Tamazov <artem.tamazov@amd.com> | 2016-04-13 16:18:41 +0000 |
| commit | eb4d5a9b0b30d6754e5308dc3650ffe609cc1d07 (patch) | |
| tree | 0863907561b5303940cb309c86d3589e44ebe83e /llvm/lib/Bitcode | |
| parent | 2f6845ba3985b6758ae00615cdc307e55b4bcafc (diff) | |
| download | llvm-eb4d5a9b0b30d6754e5308dc3650ffe609cc1d07.zip llvm-eb4d5a9b0b30d6754e5308dc3650ffe609cc1d07.tar.gz llvm-eb4d5a9b0b30d6754e5308dc3650ffe609cc1d07.tar.bz2 | |
[AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status
Tests added along with implemented feature.
Note that there is a small leftover of unecessary MI sheduling issue
(more info in the review). CodeGen/AMDGPU/salu-to-valu.ll updated to fix
the false regression.
TODO: Support for TTMP quads, comma-separated syntax in "[]" and more.
Differential Revision: http://reviews.llvm.org/D17825
llvm-svn: 266205
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions