diff options
| author | Victor Campos <victor.campos@arm.com> | 2020-03-09 13:29:37 +0000 |
|---|---|---|
| committer | Victor Campos <victor.campos@arm.com> | 2020-05-28 10:52:43 +0100 |
| commit | c010d4d195506aaea76a1cc8afb5a6b5884dba44 (patch) | |
| tree | 78c8656440ad6812bccad0d7076d5db86e48e089 /llvm/lib/Bitcode | |
| parent | 23ac16cf9bd4cc0bb434efcf6385baf083a2ff7b (diff) | |
| download | llvm-c010d4d195506aaea76a1cc8afb5a6b5884dba44.zip llvm-c010d4d195506aaea76a1cc8afb5a6b5884dba44.tar.gz llvm-c010d4d195506aaea76a1cc8afb5a6b5884dba44.tar.bz2 | |
[ARM] Improve codegen of volatile load/store of i64
Summary:
Instead of generating two i32 instructions for each load or store of a volatile
i64 value (two LDRs or STRs), now emit LDRD/STRD.
These improvements cover architectures implementing ARMv5TE or Thumb-2.
The code generation explicitly deviates from using the register-offset
variant of LDRD/STRD. In this variant, the register allocated to the
register-offset cannot be reused in any of the remaining operands. Such
restriction seems to be non-trivial to implement in LLVM, thus it is
left as a to-do.
Differential Revision: https://reviews.llvm.org/D70072
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions