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| author | Uriel Korach <uriel.korach@intel.com> | 2017-11-06 09:22:38 +0000 |
|---|---|---|
| committer | Uriel Korach <uriel.korach@intel.com> | 2017-11-06 09:22:38 +0000 |
| commit | bb86686a8b6f9433954a535f99f23e11b78ca348 (patch) | |
| tree | 7b638850534418ef4bb1e38205b3ab3e5ba44bca /llvm/lib/Bitcode | |
| parent | eb47d95d528b7e1b47137c6ad028ae93526eb548 (diff) | |
| download | llvm-bb86686a8b6f9433954a535f99f23e11b78ca348.zip llvm-bb86686a8b6f9433954a535f99f23e11b78ca348.tar.gz llvm-bb86686a8b6f9433954a535f99f23e11b78ca348.tar.bz2 | |
[X86][AVX512] Improve lowering of AVX512 test intrinsics
Added TESTM and TESTNM to the list of instructions that already zeroing unused upper bits
and does not need the redundant shift left and shift right instructions afterwards.
Added a pattern for TESTM and TESTNM in iselLowering, so now icmp(neq,and(X,Y), 0) goes folds into TESTM
and icmp(eq,and(X,Y), 0) goes folds into TESTNM
This commit is a preparation for lowering the test and testn X86 intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D38732
llvm-svn: 317465
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions