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| author | Tim Northover <t.p.northover@gmail.com> | 2021-04-21 12:12:28 +0100 |
|---|---|---|
| committer | Tim Northover <t.p.northover@gmail.com> | 2021-05-14 10:41:38 +0100 |
| commit | 4789fc75d3501f14cfbd5b102f173721d498ff58 (patch) | |
| tree | f3a1b06de28ccf02a33158620054e552d3caa850 /llvm/lib/Bitcode | |
| parent | 459c48e04f25a40a81e9e11ccb9c17a88dc39999 (diff) | |
| download | llvm-4789fc75d3501f14cfbd5b102f173721d498ff58.zip llvm-4789fc75d3501f14cfbd5b102f173721d498ff58.tar.gz llvm-4789fc75d3501f14cfbd5b102f173721d498ff58.tar.bz2 | |
AArch64: support i128 cmpxchg in GlobalISel.
There are three essentially different cases to handle:
* -O1, no LSE. The IR is expanded to ldxp/stxp and we need patterns to select
them.
* -O0, no LSE. We get G_ATOMIC_CMPXCHG, and need to produce CMP_SWAP_N
pseudos. The registers are all 64-bit so this is easy.
* LSE. We get G_ATOMIC_CMPXCHG and need to produce a CASP instruction with
XSeqPair registers.
The last case is by far the hardest, and and adds 128-bit GPR support as a
byproduct.
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions