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| author | Yeting Kuo <yeting.kuo@sifive.com> | 2023-07-07 13:47:48 +0800 |
|---|---|---|
| committer | Yeting Kuo <yeting.kuo@sifive.com> | 2023-07-14 15:45:44 +0800 |
| commit | 2ac99205ee1a232b8da5ec144662b29bb00ccd70 (patch) | |
| tree | 2c4b3ea7a5dbcc9ab90f8eb97f4eca1448e22a79 /llvm/lib/Bitcode | |
| parent | 2d6a5ab5ebd4907fe3bb2ee67574fd672ad80bd8 (diff) | |
| download | llvm-2ac99205ee1a232b8da5ec144662b29bb00ccd70.zip llvm-2ac99205ee1a232b8da5ec144662b29bb00ccd70.tar.gz llvm-2ac99205ee1a232b8da5ec144662b29bb00ccd70.tar.bz2 | |
[RISCV] Narrow types of index operand matched pattern (shl (zext), C).
(shl (zext to iXLenVec), C) is a possible pattern in auto-vectorized code for
indexed loads/stores. But extending to iXLen might be too aggressive, RVV
indexed load/store instructions zero extend their indexed operand to XLEN.
The patch tries to narrow the type of the zero extension. It's benefit to
decrease register pressure.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D154687
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions