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| author | Abhinav Garg <39309352+abhigargrepo@users.noreply.github.com> | 2025-10-31 16:45:40 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-31 16:45:40 +0530 |
| commit | 1057c63b24ec4a40beee71db5dd0dd18e43391b5 (patch) | |
| tree | 5a5b8f31ccc789e6affe9f19578d9dc002381036 /llvm/lib/Bitcode | |
| parent | 96c6fd36c1df59d1ba4bb79f22014598882acfcf (diff) | |
| download | llvm-1057c63b24ec4a40beee71db5dd0dd18e43391b5.zip llvm-1057c63b24ec4a40beee71db5dd0dd18e43391b5.tar.gz llvm-1057c63b24ec4a40beee71db5dd0dd18e43391b5.tar.bz2 | |
[AMDGPU][GlobalISel] Add register bank legalization for G_FADD (#163407)
This patch adds register bank legalization support for G_FADD opcodes in
the AMDGPU GlobalISel pipeline.
Added new reg bank type UniInVgprS64.
This patch also adds a combine logic for ReadAnyLane + Trunc + AnyExt.
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Co-authored-by: Abhinav Garg <abhigarg@amd.com>
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions