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| author | Sanjay Patel <spatel@rotateright.com> | 2021-09-24 11:31:11 -0400 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2021-09-24 11:38:19 -0400 |
| commit | 09e71c367af36a07cce04a812dcd9c62bebfbcdf (patch) | |
| tree | 39695eab5a33e5244e11e2a0b9b283c344d08b0e /llvm/lib/Bitcode | |
| parent | 638a4147fc6400b928080c6d5656fbcee707a793 (diff) | |
| download | llvm-09e71c367af36a07cce04a812dcd9c62bebfbcdf.zip llvm-09e71c367af36a07cce04a812dcd9c62bebfbcdf.tar.gz llvm-09e71c367af36a07cce04a812dcd9c62bebfbcdf.tar.bz2 | |
[x86] convert logic-of-FP-compares to FP logic-of-vector-compares
This is motivated by the examples and discussion in:
https://llvm.org/PR51245
...and related bugs.
By using vector compares and vector logic, we can convert 2 'set'
instructions into 1 'movd' or 'movmsk' and generally improve
throughput/reduce instructions.
Unfortunately, we don't have a complete vector compare ISA before
AVX, so I left SSE-only out of this patch. Ie, we'd need extra logic
ops to simulate the missing predicates for SSE 'cmpp*', so it's not
as clearly a win.
Differential Revision: https://reviews.llvm.org/D110342
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions