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| author | Ties Stuij <ties@stuij.se> | 2023-06-27 14:28:53 +0100 |
|---|---|---|
| committer | Ties Stuij <ties.stuij@arm.com> | 2023-06-27 14:58:22 +0100 |
| commit | 03db28edbb71ea62be133d478c872c5d825b7389 (patch) | |
| tree | c57423ecbbf6846420e647f1a8c05d92211a69c9 /llvm/lib/Bitcode | |
| parent | 6d6e32895b1504189d10bae20310a6c67f852fb4 (diff) | |
| download | llvm-03db28edbb71ea62be133d478c872c5d825b7389.zip llvm-03db28edbb71ea62be133d478c872c5d825b7389.tar.gz llvm-03db28edbb71ea62be133d478c872c5d825b7389.tar.bz2 | |
[ARM] in ExpandTMOV32BitImm, CPSR register ops should be `Define`d
The CPSR registers ops of the instructions constructed in ExpandTMOV32BitImm
were marked as kill, instead of define. Best to use the pre-existing
t1CondCodeOp fn to construct CPSRs.
Reviewed By: simonwallis2
Differential Revision: https://reviews.llvm.org/D153763
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions