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| author | Jay Foad <jay.foad@amd.com> | 2022-06-13 16:35:44 +0100 |
|---|---|---|
| committer | Jay Foad <jay.foad@amd.com> | 2022-06-13 21:12:11 +0100 |
| commit | bfcfd53b9244874b9807409a01407fd9e1d5d3e3 (patch) | |
| tree | 080d7360a13416999bd8fe9804189c8b06e9f2ba /llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp | |
| parent | be232979bccee6e0257bce246f0126ef26460f48 (diff) | |
| download | llvm-bfcfd53b9244874b9807409a01407fd9e1d5d3e3.zip llvm-bfcfd53b9244874b9807409a01407fd9e1d5d3e3.tar.gz llvm-bfcfd53b9244874b9807409a01407fd9e1d5d3e3.tar.bz2 | |
[AMDGPU] Add GFX11 llvm.amdgcn.permlane64 intrinsic
Compared to permlane16, permlane64 has no BC input because it has no
boundary conditions, no fi input because the instruction acts as if FI
were always enabled, and no OLD input because it always writes to every
active lane.
Also use the new intrinsic in the atomic optimizer pass.
Differential Revision: https://reviews.llvm.org/D127662
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp')
0 files changed, 0 insertions, 0 deletions