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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-11-26 19:12:18 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-26 19:12:18 -0500 |
| commit | 62584f32eb786e4c455092e653a58182e8ffe4dc (patch) | |
| tree | 5b78c0f17f28768f17168fe4adfc6f66dfc76b03 /llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp | |
| parent | 5147e5941d40ae89b6ecab89aa36f8f5def28f1e (diff) | |
| download | llvm-62584f32eb786e4c455092e653a58182e8ffe4dc.zip llvm-62584f32eb786e4c455092e653a58182e8ffe4dc.tar.gz llvm-62584f32eb786e4c455092e653a58182e8ffe4dc.tar.bz2 | |
AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_f32_{fp8|bf8} for gfx950 (#117741)
OPSEL[0] determines low/high 16 bits of src0 to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap@amd.com>
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp')
0 files changed, 0 insertions, 0 deletions