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| author | Min-Yih Hsu <min.hsu@sifive.com> | 2025-06-04 09:25:59 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-06-04 09:25:59 -0700 |
| commit | feb21e26fa0eff9c977394f04c089ea887f63b9f (patch) | |
| tree | e5ab6f53120cc72f76322a28e999ac3f4159a115 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 4b23d4c7ca4307f3d5c900782c78f1b66236d0c2 (diff) | |
| download | llvm-feb21e26fa0eff9c977394f04c089ea887f63b9f.zip llvm-feb21e26fa0eff9c977394f04c089ea887f63b9f.tar.gz llvm-feb21e26fa0eff9c977394f04c089ea887f63b9f.tar.bz2 | |
[RISCV] Add SiFive X390 processor definition (#142517)
X390 is an in-order core designed for AI/ML workload, with VLEN=1024.
https://www.sifive.com/cores/intelligence-x300-series
Scheduling model will be added in a follow-up patch.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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