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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-09-03 16:47:34 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-09-03 16:47:34 +0000 |
| commit | fb3d9e1449b1838f3ad698526dc5162c125e2064 (patch) | |
| tree | 70d81c85dd3148ab1203b3455ff553ee6a30ce4a /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 046557bc03cb9630042c8dcd4d45a4815c383e1e (diff) | |
| download | llvm-fb3d9e1449b1838f3ad698526dc5162c125e2064.zip llvm-fb3d9e1449b1838f3ad698526dc5162c125e2064.tar.gz llvm-fb3d9e1449b1838f3ad698526dc5162c125e2064.tar.bz2 | |
[X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s.
A ReadAdvance was incorrectly added to the SchedReadWrite list associated with
the following SSE instructions:
sqrtss
sqrtsd
rsqrtss
rcpss
As a consequence, a wrong operand latency was computed for the register operand
used as the base address of the folded load operand.
This patch removes the wrong ReadAdvance, and updates the llvm-mca test cases.
There is still a problem with correctly modeling partial register writes on XMM
registers This other problem is currently tracked here:
https://bugs.llvm.org/show_bug.cgi?id=38813
Differential Revision: https://reviews.llvm.org/D51542
llvm-svn: 341326
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions