diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-23 14:10:04 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-23 15:05:47 -0500 |
| commit | fac9941e57013127593a47e02e7e88f56c9be2a4 (patch) | |
| tree | 93eeed338202458238fc9a1ca92d2cb738041b20 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | b749af6a1ff45434011278c3ba765a41f0ee02f2 (diff) | |
| download | llvm-fac9941e57013127593a47e02e7e88f56c9be2a4.zip llvm-fac9941e57013127593a47e02e7e88f56c9be2a4.tar.gz llvm-fac9941e57013127593a47e02e7e88f56c9be2a4.tar.bz2 | |
AMDGPU: Fix ubsan error
Since register classes go up to 1024, 32 elements, all masks bits are
needed and a 32-bit shift by 32 is illegal. We didn't have any
instructions theoretically using a 32 element VGPR before
d1dbb5e4718a8f845abf0783513a33a55429470b
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions