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| author | Igor Breger <igor.breger@intel.com> | 2017-03-28 09:35:06 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2017-03-28 09:35:06 +0000 |
| commit | f580fce2c34461433e404b5dacad87a483d1164e (patch) | |
| tree | 5c533c1f5f9e146363ca5289e657ce8be4ae3cb9 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 923e574bff006ea6a6888e1900ecc4d4a2a4ef41 (diff) | |
| download | llvm-f580fce2c34461433e404b5dacad87a483d1164e.zip llvm-f580fce2c34461433e404b5dacad87a483d1164e.tar.gz llvm-f580fce2c34461433e404b5dacad87a483d1164e.tar.bz2 | |
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions